Positive and Negative Logic

Introduction

What does it mean that the following is an AND gate?

and-gate.gif (392 bytes)

The truth table shows that the output is 1 only when both inputs are 1, but this is the logical operation. You can't write "1" on a piece of paper and try to stuff it into the pins on the side of the IC.

The gate of course accepts inputs and produces outputs in terms of voltage levels. The truth table on the right shows the behavior you might expect from an AND gate. L stands for low voltage (0-.4 volts) and H stands for high voltage (2.8-5 volts). (The precise range is determined by the logic family the gate comes from.)

The table on the right describes an AND gate if you interpret L as logical 0 and H as logical 1. However, there is no reason you can't assume the opposite assignment--that is L is logical 1 and H is logical 0.

The freedom to interpret voltage levels leads to two two types of logic circuits: positive logic and negative logic.

x y output
L L L
L H L
H L L
H H H

 

The table below shows the two assignments that define positive and negative logic systems.

Positive Logic Negative Logic
H = 1 H = 0
L = 0 L = 1

The logical interpretation of a gate depends on whether positive or negative logic is assumed. For example:

Gate Behavior Positive Logic Negative Logic
X Y F X Y AND X Y OR
L L L 0 0 0 1 1 1
L H L 0 1 0 1 0 1
H L L 1 0 0 0 1 1
H H H 1 1 1 0 0 0

The key to understanding the concept of positve and negative logic is to recognize the difference between a logical Boolean operation and a physical implementation. Gates are physical implementation.

A logical operation has two different implementations depending on if positive or negative logic is used:

logical-physical.gif (19488 bytes)

A physical gate has two different interpretations depending on if positive or negative logic is used:

physical-logical.gif (20965 bytes)

Positive logic inputs and outputs are also called active high. Negative logic inputs and outputs are called active low. Input and output polarity is indicated by a bubble or triangle. For example, the following shows a positive logic AND gate and a negative logic OR gate. You can see from the truth table above these describe the same physical component.

pos-neg-gates.gif (759 bytes)

Example 1. Show that a positive logic XOR gate is equivalent to a negative logic XNOR gate.

The following truth table shows they are equivalent. The gate behavior is determined by the positive logic behavior of XOR. The negative logic interpretation of the gate behavior results in the XNOR gate.

Positive Logic Gate Behavior Negative Logic
X Y XOR X Y F X Y XNOR
0 0 0 L L L 1 1 1
0 1 1 L H H 1 0 0
1 0 1 H L H 0 1 0
1 1 0 H H L 0 0 1

Example 2. Show the symbol for an alarm buzzer that has one input X which is active low.

An active low input is indicated by a bubble at the input. In this context the implication is that the input X is normally high or has a voltage between 2.8 and 5 volts placed on it. When the voltage drops to the range 0-.2 volts the alarm will sound. The alarm is active low.

buzzer.gif (589 bytes)

Here is one more example of how positive and negative logic is used in practice. The following component is a D-type flip-flop:

d-flip-flop.gif (783 bytes)

D-Type Flip-Flop with asynchronous preset and clear inputs

A flip-flop is a memory element. We will study them thoroughly when we talk about sequential circuits. For the purposes of this example we are more interested in the two asynchronous inputs: prs and clr. prs or preset is used to initialize the contents of the flip-flop to 1. prs is active low which means that when this input receives a low voltage the value of the flip-flop is initialized to 1. clr or clear is used to initialize the contents of the flip-flop to 0. clr is also active low which means that when this input receives a low voltage the value of the flip-flop will be initialized to 0.

In this next example we add a NOR gate so that the clear signal can be controlled by the two inputs X and Y. X and Y are both active high. If either X or Y is high the value of the flip-flop will be cleared. You can also think of the NOR gate as an active low OR gate.

d-flip-flop-with-nor.gif (1933 bytes)

To preserve our sanity throughout the course positive logic will be assumed.